Generally, in semiconductor memory devices such as a DRAM (Dynamic Random Access Memory), a memory cell region is divided into a plurality of banks. Each bank is configured to be independently operable (see Japanese Patent Application Laid-Open No. 2000-113670 and Japanese Patent Application Laid-Open No. H11-16348). Thereby, it becomes possible to start a read operation from or a write operation into a different bank while the read operation or the write operation is executed on a certain bank. Thus, a high-speed data transfer is achieved.
A general bank arrangement is as shown in FIG. 11. Such an arrangement is suitable to a case where a pad electrode region 10 is arranged between the banks. However, in some products, pad electrode regions 11 and 12 are occasionally arranged at ends of a chip as shown in FIG. 12. The arrangement is often adopted when a data I/O width is large. When the arrangement shown in FIG. 12 is adopted, a data bus connecting an I/O pad DQ and a peripheral circuit region located between the banks (not shown) are long, and a plurality of data to be simultaneously inputted or outputted pass by way of data buses that differ in length. As a result, there occurs a problem in that a data transfer speed decreases.
For example, when the data I/O width is 2n bits, and 2n bits of data are read via n of input/output pads DQ arranged in the respective pad electrode regions 11 and 12, n bits of data read from a bank #0 to the side of the pad electrode region 11 pass by way of a relatively short data bus while remaining n bits of data read from the bank #0 to the other side of the pad electrode region 12 pass by way of a relatively long data bus.
Accordingly, when the pad electrode regions 11 and 12 are arranged in the ends of the chip as shown in FIG. 12, it is desired that each bank is positioned in an aligning manner between the pad electrode regions 11 and 12, as shown in FIG. 13. With this arrangement, it becomes possible to assign n of input/output pads DQ arranged in the pad electrode region 11 to a sub-bank region 21 located on the side of the pad electrode region 11, and assign remaining n of input/output pads DQ arranged in the pad electrode region 12 to a sub-bank region 22 located on the side of the pad electrode region 12. As a result, it becomes possible to shorten the data bus, and redress imbalance of the data bus length.
On the other hand, to operate each bank in parallel, an address supplied to each bank needs to be latched at some stage. Accordingly, in general, as shown in FIG. 14, row-address latch circuits 30 to 33, predecoders 40 to 43, and main decoders 50 to 53, which correspond to each bank, are arranged respectively.
FIG. 15 is a schematic layout diagram of an example in which a circuit configuration shown in FIG. 14 is applied to a semiconductor memory device of which banks are positioned in an aligning manner.
In the example shown in FIG. 15, the row-address latch circuits 30 to 33 and the predecoders 40 to 43 are arranged between the sub-bank regions 21 and 22, and the main decoders 50 to 53 are arranged between banks #0 and #1 and banks #2 and #3, respectively.
However, when such a layout is adopted, there is a problem in that the number of buses connecting the predecoders 40 to 43 and the main decoders 50 to 53 increases. For a more specific explanation, considered is a case in which out of the row address, a portion for selecting a memory mat within the bank is XMAT, a portion for selecting a main word line is XMWL, a portion for selecting a sub word line is XSWL; and each portion is a-bits, b-bits, and c-bits. Further, assume that predecoding is performed by dividing the portion XMAT for selecting the memory mat into a1 high-order bit and a2 low-order bits; and dividing the portion XMWL for selecting the main word line into b1 high-order bit and b2 low-order bits.
In this case, the number of predecode signals, which are outputs of the predecoders 40 to 43, is 2a1+2a2+2b1+2b2+2c. As an example, when a1=2 bits, a2=2 bits, b1=3 bits, b2=3 bits, and c=2 bits are established, the number of predecode signals is 28. That is, each of the predecoders 40 to 43 and the main decoders 50 to 53 needs to be connected by 28 buses.
Further, as shown in FIG. 15, between the banks, two main decoders 50 and 51 or 52 and 53 that correspond to the banks on the both sides (for example, the bank #0 and the bank #1) are arranged. Thus, the buses for the predecode signal that is formed between the banks are 56 in total (=2×28), and as a result, a wire pitch becomes very narrow.
In addition, in the circuit configurations shown in FIGS. 14 and 15, the row address is latched in each bank. Thus, a delay by a latch margin (tRCD) occurs, and this leads to a problem in that an operating margin becomes small.